In complementary metal oxide semiconductor (CMOS) technologies, process variations during manufacturing have a significant impact on circuit performance, such as timing. The effect of these variations worsens as minimum feature sizes scale down and as circuit complexity and die sizes increase. In many of today's integrated circuit design implementation flows, variability in devices and interconnects is modeled by timing analysis and optimization of a design at multiple process corners.
Generally speaking, timing analysis calculates circuit timing delays and ensures that those delays are within bounds as specified by user constraints. There are two major types of timing analyses, namely, static timing analysis (referred to as “STA”) and dynamic timing analysis. Static timing analysis calculates the individual delays associated with different portions of a circuit and then generates a report detailing the minimum and maximum delays associated with each possible path and whether those delays meet user constraints. On the other hand, dynamic timing analysis typically specifies an event that may occur sometime within a certain time period and then determines the timing along different paths of the circuit in response to the event.
In conventional static timing analysis, models at various process corners have significant pessimism built into them. Generally speaking, pessimism refers to the extra timing margin (e.g., extra delay margin) added to make it more likely that a device in the circuit is going to satisfy specified timing requirements. As the built-in pessimism of the models is reduced, the reported worst-case timing slack for the circuit typically improves.
With shrinking technology, timing closure has become difficult because it is now possible to pack more functionality on a smaller die, resulting in multiple modes of running the chip. In addition to multiple modes, process variations may require multiple corners, and complex architecture may require multiple modes to be analyzed, and as a result the timing closure in all the corners has become a very time-consuming process. With new technologies like multi-mode multi-corner (MMMC) analysis, the whole process of timing closure has become overly exhaustive, time consuming, and costly.
A typical chip has large number of input/output (“I/O”) interfaces, for example, audio, serial, or Ethernet. However, not all interfaces can be analyzed together or under the same conditions. Port multiplexing may be performed to achieve different functionalities in different I/O modes. The same port may get different delay constraints, case values, clock or data signals depending on the I/O mode.
Many design configurations have a large number of I/O modes. Indeed, there are often more I/O modes than functional modes. Users of STA tools generally understand this and try to reduce the amount of STA work needed in various ways, such as by merging modes to reduce number of I/O modes, or by trying to add some internal register-to-register constraints to disable timing along certain paths.
These user-driven approaches are common and provide some usefulness, but current timing tools are still limited in that they are not tailored to limit the analysis to an active zone of timing paths only, and instead still require a full STA analysis. Moreover, these user-driven approaches are overly complex and have multiple problems. Specific user-driven approaches involve constraint sets that are much more complex and which degrade performance. For example, such user-driven approaches use too many extra constraints (for example, setting false paths, setting clock groups, clock duplication) to attempt to disable the non-I/O network. This manual intervention from the user is also prone to errors that result in either missing constraints or applying the wrong constraints, which may disable real I/O paths. Current user driven approaches also require a large amount of constraint debugging ability to attempt to ensure the correctness of the manual constraint generation. These approaches suffer a further drawback in that the timing tool is not aware of user's real intent and hence still proceeds with a complete loading of the design loading, complete loading of parasitic information (usually in the form of “Standard Parasitic Exchange Format,” or “SPEF”), delay calculation, and/or analysis of the full design resulting in an overly large number of MMMC views. In addition, user reporting scripts becomes too complex as they try to use too many I/O group_path constraints or use complex report_timing commands (using report_timing-from/through/to option) to focus on I/O paths only.
As digital circuit components have gotten smaller, the number of process corners has increased exponentially, now often ranging from 10-20 corners or more per analysis mode. With this increased number of corners, full chip analysis for all the modes may become unworkable as a large number of STA runs have a large bearing on design timing closure cycle. The increased number of corners can also lead to a larger number of design changes since the number of variables affecting timing have increased.
Also, analyzing signal integrity (“SI”) effects during a large number of STA cycles adds another performance bottleneck to the system analysis. Chip designers typically do not run SI analysis for all I/O modes because they do not have sufficient time in their design cycle. Instead chip designers tend to put high guard bands (timing derates) to add pessimism that can cover SI effects. However, this can have a bearing on the overall quality of results of the design.
Although the present methods are useful to a degree, there still exists a need in the field for reduced runtime, reduced error, and reduced memory STA runs. Thus, for at least these reasons there is a need for more accurate and efficient methods and systems for MMMC STA runs for I/O modes.